system verilog - When to use define macro vs generate -

what guidelines choosing generate statements on `define macros , vice versa in systemverilog?

for example, if want conditionally instantiate either module1 or module2, seems can either do

`ifdef cond1 module1 (); `else module2 (); 

or

generate if (cond1) begin module1 (); end else begin module2(); end endgenerate 

people have differing opinions, 1 big difference between 2 generates allow different instances configured differently, macros not. because generates evaluated @ elaboration, rather @ compile time.

for example, if have module:

module ahwoogaa #(bit cond1) ();    generate     if (cond1) begin       module1 ();     end else begin       module2();     end   endgenerate  endmodule 

i can instantiate twice cond1 so:

module neeenaaaw();    ahwoogaa #(1'b0) alarm1();   ahwoogaa #(1'b1) alarm2();  endmodule 

with define have have single value of cond1 instances, set value once when compile module.

personally go generates whenever can.