makefile - Automatically generating dependency in make and including them in dependency list -

here tutorial explains quite beautifully , of works fine. following final makefile tutorial assumes have directory structure following:

root-----makefile    |-----all source files here. 

results of compilation in root directory. following makefile:

objs := foo.o bar.o  # link proggie: $(objs)     gcc $(objs) -o proggie  # pull in dependency info *existing* .o files -include $(objs:.o=.d)  #note  %.o: %.c   #note     gcc -c $(cflags) $*.c -o $*.o     gcc -mm $(cflags) $*.c > $*.d     @cp -f $*.d $*.d.tmp @sed -e 's/.*://' -e 's/\\$$//' < $*.d.tmp | fmt -1 | \   sed -e 's/^ *//' -e 's/$$/:/' >> $*.d @rm -f $*.d.tmp # remove compilation products clean:     rm -f proggie *.o *.dobjs := foo.o bar.o 

i not understand 1 thing in tutorial. says pull in dependency info *existing* .o files , corresponding .d files made how these taken care of no change has been made in dependency list of targets still remain %.o: %.c.

in fact have noticed not work me. can explain going on here. if tutorial wrong(which highly doubt) please mention how can include dependency .d files dependency list.

the dependency files created gcc mm contain rules like:

foo.o: stdio.h myinc.h # ... 

and line here includes dependency file each object in list:

-include $(objs:.o=.d) 

just @ foo.d example.

according this:

one file can target of several rules. prerequisites mentioned in rules merged 1 list of prerequisites target. if target older prerequisite rule, recipe executed.

so if have rule %.o: %.c, include statement imports rules expand rule dependencies.