vhdl - compare two clock signals -

we designing robot university project group, first year electrical engineering students. robot has detect mines simple lc oscillator en comparator. output of circuit block wave our fpga can count specified number , compare pre defined number, see if there change in frequency of oscillator (meaning there metal object under sensor). wrote seams rising_edge(sensor) not work, dont understand because both counter practically same. entity of clock same, clock input.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity metaal_detector   port(     sensor, reset: in std_logic;     sensor_out: out std_logic_vector(10 downto 0)  );  end entity metaal_detector;   architecture behavioural of metaal_detector signal  count, new_count    : unsigned (10 downto 0);  begin process (sensor) begin     if (rising_edge (sensor))         if (reset = '1')             count   <= (others => '0'); -- zet op 0 bij reset         else             count   <= new_count;         end if;     end if; end process;  process (count) begin     new_count   <= count + 1;    end process;  sensor_out  <= std_logic_vector (count); end architecture behavioural; 

this testbench:

 library ieee;  use ieee.std_logic_1164.all;   entity testbench  end entity testbench;   architecture test of testbench    component sensor_control     port(     clk, reset, sensor: in std_logic;    metaal: out std_logic;    reset_teller: out std_logic    );  end component;    component counter    port(    clk, reset: in std_logic;    count_out: out std_logic_vector(10 downto 0)    );  end component;   component metaal_detector   port(  sensor, reset: in std_logic;  sensor_out: out std_logic_vector(10 downto 0)  );  end component;    signal sensor, clock, reset, metaal, reset_teller: std_logic;     signal count1, sensor1: std_logic_vector(10 downto 0);     begin    clock <=       '1' after  0 ns,              '0' after 10 ns when clock /= '0' else '1' after 10 ns;     reset   <=       '1' after 0 ns,                      '0' after 35 ns;     sensor   <=  '1' after  0 ns,              '0' after 30 ns when sensor /= '0' else '1' after 30 ns;    lblb0: sensor_control port map (clock, reset, sensor, metaal, reset_teller);                         lbl0: counter port map(clock, reset_teller, count1);  lbl1: metaal_detector port map(sensor, reset_teller, sensor1);  end architecture test; 

if use clk instead of clock somewhere because if trying many things.

appreciate if explain doing wrong.

david kester

you don't need seperate "new_count" stuff "count" stuff... combine them 1 process! counter (with synchronous reset) implemented follows:

process (clock)  begin    if rising_edge(clock)       if reset='1'           count <= (others => '0');       else      -- or, clock enable:  elsif clock_enable='1'          count <= count + 1;       end if;    end if; end process;