How to read a text file line by line in verilog? -

i have srec file simple text file , want read line line in verilog. how can that?

the following reads through file, 1 line per clock cycle: expected data format 1 decimal number per line.

integer               data_file    ; // file handler integer               scan_file    ; // file handler logic   signed [21:0] captured_data; `define null 0      initial begin   data_file = $fopen("data_file.dat", "r");   if (data_file == `null) begin     $display("data_file handle null");     $finish;   end end  @(posedge clk) begin   scan_file = $fscanf(data_file, "%d\n", captured_data);    if (!$feof(data_file)) begin     //use captured_data other wire or reg value;   end end