vhdl - Getting wrong results in post synthesis simulation -

i writing code matrix transpose in vhdl taking input in row major , 1 element of matrix per every clock cycle , store data in column major format after send tha data in coloumn major format element element every clock cycle output . code below simulating post synthesis results not right can plz how synthesize code correct results

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity matrix_trans_sysgen generic(n: integer :=3); port (my_clk : in std_logic; my_ce : in std_logic; input_matrix : in std_logic_vector(5 downto 0); output_matrix : out std_logic_vector(5 downto 0) ); end matrix_trans_sysgen;  architecture behavioral of matrix_trans_sysgen  type t1 array (natural range<>) of std_logic_vector(5 downto 0);  signal : t1((n*n)-1 downto 0) :=(others => (others =>'0'));  signal output_there : std_logic :='0';  signal x : integer range 0 2*n :=0; signal y : integer range 0 2*n :=0; signal z : integer range 0 2*n*n :=0;  begin  ----- process take input_matrix array process(my_clk,input_matrix,x,y) begin  if(x < n)      if(y < n)        if(rising_edge(my_clk))            a(y*n+x) <= input_matrix;           y <= y+1;        end if;     else       x<=x+1;       y<=0;     end if;   else     output_there <= '1';  end if; end process;   ----- process send output elements through port process(my_clk,z,output_there) begin  if (output_there = '1')      if(z < n*n)         if(rising_edge(my_clk))            output_matrix <= a(z);          z<=z+1;        end if;      end if;  end if;  end process;  end behavioral; 

thanks , regards

teja

rewrite using usual template clocked processes. is,

"if rising_edge(clk) ... "

outermost in process. synthesis tools construct , handle correctly; other forms of process can confuse tools.