vhdl - Warning: Design contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) -


i'm having warning while syn. vhdl code synopsys design compiler. how can eliminate warning ?

it's useful warning : , it's warning not error : why want eliminate it?

1) high fanout expected? if not, find out why it's occurring, , if turns out come mistake, (i wanted 1 register, not 32!) fix it.
2) if high fanout real , can tolerate slow timings result, increase fanout limit in synthesis tool.
3) if high fanout real , can not tolerate slow timings, check tool replicating signal enough times reduce fanout , improve timings. report duplicated signals somewhere.

4) if process requires remove every synthesis warning (and have never worked anywhere case) replicate signals (and add synthesis attributes prevent removal!) reduce fanout enough eliminate warning. leads messy, hard maintain designs.


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