styles - what is the difference between the following to coding in VHDL to update registers? -

could ask difference between following 2 coding styles? first 1 read xilinx sample code. second, read book teaching vhdl.

1. signal: register std_logic；    signal: output std_logic;    process (clk)    begin     if rising_edge(clk)       register <= outside_signal ;      end if;    end process;     output <= register;  2. signal: register_reg    std_logic;    signal: register_next   std_logic;    signal: output std_logic;    process (clk)    begin     if rising_edge(clk)       register_reg <= register_next;      end if;    end process;    register_next<=outside_signal;    output <= register_reg; 

thank much.

the obvious difference intermediate signal register_next declared , driven outside_signal signal, instead of using outside_signal directly in process.

the simple answer there no functional difference. (complex answer register_next<=outside_signal delays signal delta delay (not actual time delay), delta delay typically not visible don't worry if don't understand concept.)

from coding style point of view, "renaming" of of signal through register_next<=outside_signal construction should avoided, since confusing read code signals same functional behavior , same origin called different names.

also, coding style point of view suggest name of signal driven clocked process, , name of output, have defined similarity. suggest output called example result_o, , internal signal updated process called result. internal intermediate signal required vhdl-2002 if result read in module, , output port assigned result_o <= result. when code read, thereby easier understand result_o , result related. code:

process (clk) begin  if rising_edge(clk)    result <= outside_signal;  end if; end process; result_o <= result; 

btw. "register" reserved vhdl keyword, can't use signal identifier.