makefile - Automatic dependency list not generated in a different setting of directory structure -
i have following directory structure:
root-----makefile |-----src #all source files here. |-----obj #all object files here. |-----bin #the final target. the contents of makefile given below:
target = exec cc = gcc cflags = -g -i. linker = gcc -o lflags = -i. -lm -lpthread bindir = bin objdir = obj srcdir = src interface = interface std = -std=c99 programsources := $(wildcard $(srcdir)/*.c) programinterface:= $(wildcard $(interface)/*.h) objects := $(programsources:$(srcdir)/%.c=$(objdir)/%.o) $(bindir)/$(target) : $(objects) $(linker) $@ $(lflags) $(objects) $(std) #pull dependencies .o files -include $(objects:.o=.d) $(objects) : $(objdir)/%.o :$(srcdir)/%.c $(cc) $(cflags) -c $< -o $@ $(std) $(cc) $(cflags) -mm $< > $*.d @mv -f $*.d $*.d.tmp @sed -e 's|.*:|$(objdir)/$*.o:|' < $*.d.tmp > $*.d @sed -e 's/.*://' -e 's/\\$$//' < $*.d.tmp | fmt -1 | \ sed -e 's/^ *//' -e 's/$$/:/' >> $*.d` @rm -f $*.d.tmp` .phony : run run :` ./$(bindir)/$(target) ${type} ${inp_file} i have used tutorial here have been modified suit corresponding directory structure. has got wrong in modification , cannot understand what. dependency list generated in .d files not taken account i.e. if change .h rules not compiling.
you appear producing dependency files in root/, looking them in obj/.
try changing this:
-include $(objects:.o=.d) to this:
-include *.d there other improvements can make, once makefile working.
edit: further improvements
1) choice of put dependency files arbitrary, if put them in obj/, can simplify $(objects) rule quite lot:
-include $(objdir)/*.d $(objects): $(objdir)/%.o :$(srcdir)/%.c $(cc) $(cflags) -mmd -mp -c $< -o $@ $(std) 2) programinterface , interface aren't used, can remove them.
3) putting -o in linker dangerous. , don't forget automatic variable $^:
linker = gcc $(bindir)/$(target) : $(objects) $(linker) $@ $(lflags) $^ $(std) 4) wise give run prerequisite:
run: $(bindir)/$(target) ./$< ${type} ${inp_file}
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